ISL12022MIBZR5421【PDF 9/31 页】IC RTC/CALENDAR TEMP SNSR 20SOIC

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ISL12022MR5421

FN7576.3

June 7, 2012

Interrupt Control Register (INT)

AUTOMATIC RESET BIT (ARST)

This bit enables/disables the automatic reset of the ALM, LVDD,

LBAT85, and LBAT75 status bits only. When ARST bit is set to “1”,

these status bits are reset to “0” after a valid read of the

respective status register (with a valid STOP condition). When the

ARST is cleared to “0”, the user must manually reset the ALM,

LVDD, LBAT85, and LBAT75 bits.

WRITE RTC ENABLE BIT (WRTC)

The WRTC bit enables or disables write capability into the RTC

Timing Registers. The factory default setting of this bit is “0”.

Upon initialization or power-up, the WRTC must be set to “1” to

enable the RTC. Upon the completion of a valid write (STOP), the

RTC starts counting. The RTC internal 1Hz signal is synchronized

to the STOP condition during a valid write cycle.

INTERRUPT/ALARM MODE BIT (IM)

This bit enables/disables the interrupt mode of the alarm

function. When the IM bit is set to “1”, the alarm will operate in

the interrupt mode, where an active low pulse width of 250ms

will appear at the IRQ/FOUT pin when the RTC is triggered by the

alarm, as defined by the alarm registers (0Ch to 11h). When the

IM bit is cleared to “0”, the alarm will operate in standard mode,

where the IRQ/FOUT pin will be set low until the ALM status bit is

cleared to “0”.

FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB)

This bit enables/disables the IRQ/FOUT pin during battery

backup mode (i.e. VBAT power source active). When the FOBATB

is set to “1”, the IRQ/FOUT pin is disabled during battery backup

mode. This means that both the frequency output and alarm

output functions are disabled. When the FOBATB is cleared to

“0”, the IRQ/FOUT pin is enabled during battery backup mode.

Note that the open drain IRQ/FOUT pin will need a pull-up to the

battery voltage to operate in battery backup mode.

FREQUENCY OUT CONTROL BITS (FO <3:0>)

These bits enable/disable the frequency output function and

select the output frequency at the IRQ/FOUT pin. See Table 5 for

frequency selection. Default for the ISL12022MR5421 is FO<3:0>

= 1h, or 32.768kHz output (FOUT is ON). When the frequency mode

is enabled, it will override the alarm mode at the IRQ/FOUT pin.

Power Supply Control Register (PWR_VDD)

CLEAR TIME STAMP BIT (CLRTS)

This bit clears Time Stamp VDD to Battery (TSV2B) and Time

Stamp Battery to VDD Registers (TSB2V). The default setting is 0

(CLRTS = 0) and the Enabled setting is 1 (CLRTS = 1).

VDD BROWNOUT TRIP VOLTAGE BITS (VDDTRIP<2:0>)

These bits set the trip level for the VDD alarm, indicating that VDD

has dropped below a preset level. In this event, the LVDD bit in

the Status Register is set to “1”. See Table 7.

TABLE 3. INTERRUPT CONTROL REGISTER (INT)

ADDR

321

08h

ARST

WRTC

FOBATB

FO3 FO2 FO1 FO0

TABLE 4. IM REGISTER

IM BIT

INTERRUPT/ALARM FREQUENCY

Single Time Event Set By Alarm

Repetitive/Recurring Time Event Set By Alarm

TABLE 5. FREQUENCY SELECTION OF IRQ/FOUT PIN

FREQUENCYFOU

UNITS

FO3

FO2

FO1

FO0

0Hz

32768

4096

1024

8Hz

4Hz

2Hz

1Hz

1/2

1/4

1/8

1/16

1/32

TABLE 6. CLRTS REGISTER

ADDR

09h

CLRTS

VDDTrip2 VDDTrip1 VDDTrip0

TABLE 7. VDD TRIP LEVELS

VDDTrip2

VDDTrip1

VDDTrip0

TRIP VOLTAGE

(V)

2.295

2.550

2.805

3.060

4.250

4.675

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